1. Field of the invention
This invention relates to a nonvolatile semiconductor memory device, and more particularly to a circuit for verifying newly programmed data, based on stored data, immediately after a data programming operation.
2. Description of the related art
Conventional ultraviolet erasable and programmable read only memories (EPROMs), make use of a 1system for data storage; that is, each memory cell formed of a floating gate type transistor is used to store one-bit data. With an increase in the operation speed of the central processing unit (CPU) used in recent computer systems, requirements for high speed for the EPROM have become stronger. In order to meet the requirement a 2-cell/1-bit type or 4-cell/1-bit type EPROM has been proposed. The above type EPROM is disclosed in, for example, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-20. No. 5, OCT., 1985, pp. 162, 163 and 332 "A 25-ns 16K CMOS PROM Using a FourTransistor Cell and Differential Design Technique" Saroj Pathak et. al. In the 2-cell/1bit type EPROM, differential amplification type sense amplifier SA as shown in FIG. 1 is used. Sense lines SL and SL, loads 31 and 32, bit line potential clamping transistors 33 and 34, common bit lines CL and CL, column selection transistors 35 and 36, bit lines BL and BL, and memory cells MC and MC are respectively arranged symmetrically with respect to sense amplifier SA. That is, load 31, the current path of clamping transistor 33, common bit line CL, the current path of column selection transistor 35, bit line BL and the current path of memory cell MC are series-connected between power sources Vcc and Vss. Further, a connection node between load 31 and clamping transistor 33 is connected to one end of sense line SL which is connected at the other end to a first input terminal of sense amplifier SA. Likewise, load 32, the current path of clamping transistor 34, common bit line CL, the current path of column selection transistor 36, bit line BL and the current path of memory cell MC are series-connected between power sources Vcc and Vss. Further, a connection node between load 32 and clamping transistor 34 is connected to one end of sense line SL which is connected at &he other end to a second input terminal of sense amplifier SA. The gates of clamping transistors 33 and 34 are supplied with bias voltage VB. The gates of column selection transistors 35 and 36 are supplied with the same column selection signal. The control gates of memory cells MC and MC are supplied with the same word line selection signal The mutual conductances gm of loads 31 and 32 are set at the same value, and clamping transistors 33 and 34 and column selection transistors 35 and 36 are formed with the same size.
The programming operation of the EPROM is effected under the condition that a memory cell connected to one bit line is set in the programmed state (off condition) and a memory cell connected to the other bit line is set in the non-programmed state (on condition). One of the memory cells is selectively set into the programmed state (turned on) according to data to be programmed. As a result, complementary data are programmed into memory cells MC and MC. In the data readout mode, whether stored data is "1" or "0" is determined according to the magnitude of the potentials read out from memory cells MC and MC and supplied to bit lines BL and BL. In this case, the potentials of sense lines SL and SL are determined by the resistance ratio between the resistances of loads 31 and 32 and the resistances of memory cells MC and MC. Complementary data are stored in memory cells MC and MC, and mutual conductances gm thereof are different. Therefore, a potential difference occurs between sense lines SL and SL without fail. The potential difference is amplified by means of sense amplifier SA and then output as readout data.
As described above, according to the 2-cell/1-bit type EPROM, the potentials of sense lines SL and SL are set to different potential levels, high/low or low/high, so that the noise margin can be enlarged and the design suitable for high speed operation can be easily obtained.
In most cases, loads 31 and 32 of the circuit shown in FIG. 1 are each formed using P-channel enhancement type MOS transistor 41 having the gate and drain connected together as shown in FIG. 2. The relation between potentials of sense lines SL and SL obtained in this case and the potential of power source Vcc is shown in FIG. 3. FIG. 3 shows the relation between the potentials with shift amount .DELTA.VTH (which is a threshold voltage raised from the initial voltage by programming data to inject electrons into the floating gate electrode, and corresponds to the amount of programming charges) of the threshold voltage of memory cells MC and MC used as a parameter. The potential of the sense line (for example, SL) associated with memory cell MC set in the programmed state becomes higher than that of the sense line associated with memory cell MC set in the non-programmed state. A difference between the potentials (sense line potentials) becomes smaller as the potential of power source Vcc is raised, but the potential level relation thereof will not be reversed. Further, as shown in FIG. 4, the potential of the sense line associated with memory cell MC set in the programmed state becomes higher as the amount of programming charges .DELTA.V.sub.TH in the memory cell set in the programmed state is larger while the potential of power source Vcc is set at a constant level. Therefore, as the amount of programming charges .DELTA.V.sub.TH is larger, the difference between the sense line potentials becomes larger. In general, when the difference between the sense line potentials is supplied to sense amplifier SA, the amplification operation of sense amplifier SA is effected more stably and quickly as the difference between the sense line potentials is larger, thus improving the access time and noise margin.
In the conventional 1-cell/1-bit type EPROM, in order to attain a sufficiently large amount of charges programmed into the memory cell, it is common practice to set the voltage level (6.25 V, for example) of power source Vcc at the programming time relatively higher than that (5 V) of power source Vcc at the readout time. Further, the drain and control gate of a memory cell to be programmed are supplied with high level programming voltage Vpp (12.75 V). The verify operation is effected immediately after the programming operation, and the same voltage of power source Vcc as is used in the programming mode is used when it is checked whether or not the programming operation is satisfactorily effected. If it is detected that the programming operation is not effected satisfactorily, an additional programming operation is effected until a sufficiently large amount of programming charges is obtained. It is required to set a severe criterion for the programming charge amount in the verify operation in order to not only enlarge the noise margin but also enlarge the process margin including the reliability. The requirement is proposed in consideration of the possibility that the stored charges in the floating gate electrode of the EPROM will be lost after data is programmed, and the threshold voltage is lowered. The loss of programmed charges may be caused by the following two reasons: The first reason is that when data is programmed into a memory cell which is connected to the same bit line or word line of the memory cell array to which the memory cell having data stored in the preceding cycle is connected, an intense electric field is applied between the floating gate electrode and drain region or between the control gate electrode and floating gate electrode of the memory cell having data stored in the preceding cycle, thereby causing part of charges stored in the floating gate electrode of the data storing memory cell to be emitted along the electric field. The second reason is that the charge is lost when it is operated over a long period of time, for example, for several years.
However, unlike the 1-cell/1-bit type EPROM, in the 2-cell/1-bit type EPROM shown in FIG. 1, it is difficult to set the voltage level of power source Vcc to a high voltage level in order to ensure that data can be programmed with a sufficiently large amount of programming charges. This is because, when programming charge amount .DELTA.V.sub.TH of memory cell MC associated with one sense line (for example, SL) is small, 0 V, for example, in the 2-cell/1-bit type EPROM, the slightest amount of programming charges programmed into memory cell MC associated with the other sense line (SL) may cause the potential of sense line SL to be set higher than that of sense line SL. The potential level relation between the potentials of the sense lines will not be reversed even when the voltage level of power source Vcc is raised. Therefore, even if the voltage level of power source Vcc is raised, it is impossible to ensure sufficiently large programming charge amount .DELTA.V.sub.TH. When programming charge amount .DELTA.V.sub.TH becomes insufficient, the characteristics of access time t.sub.ACC and the noise margin will be degraded. Further, the loss of slight amount of programming charges may change data in the memory cell.
As described above, in the case of the EPROM using two sets of memory cells for each bit, it is impossible to ensure a sufficiently large amount of programming charges in the memory cell by simply setting the voltage level of power source Vcc higher in the programming mode than in the readout mode, thereby providing various problems.